J. Alvarez, Hector Sanchez, G. Gerosa, C. Hanke, Roger Countryman, S. Thadasina
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引用次数: 1
摘要
介绍了一种采用0.5 μm CMOS技术实现的3.3 V锁相环(PLL)时钟合成器。锁相环支持1、1.5、2、3和4的内部到外部时钟频率比，以及PowerPC微处理器的许多静态断电模式。CPU时钟锁定范围从6到175 MHz。锁相时间小于15 μs，锁相功耗小于10 mW，相位误差和抖动小于±100 ps。锁相环的总面积为0.52 mm 2
A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL support internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2
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