{"title":"用于开关稳压器的电压比较器的设计","authors":"Yuanjie Bin, F. Quanyuan","doi":"10.1109/ICASIC.2007.4415715","DOIUrl":null,"url":null,"abstract":"In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair; middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6 um CMOS technologies and 3.6 V power supply.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a voltage comparator using for switching regulator\",\"authors\":\"Yuanjie Bin, F. Quanyuan\",\"doi\":\"10.1109/ICASIC.2007.4415715\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair; middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6 um CMOS technologies and 3.6 V power supply.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415715\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种用于开关稳压器的比较器。本设计采用负反馈结构的偏置级，以获得更稳定的直流偏置电压。所述比较器由3级组成:输入级、射极耦合差分对;中间级为折叠级联放大器，输出级由有源负载逆变器组成。本文所示的仿真结果是通过Hspice采用0.6 um CMOS技术和3.6 V电源得到的。
Design of a voltage comparator using for switching regulator
In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair; middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6 um CMOS technologies and 3.6 V power supply.
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