A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells

An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to increase TDC resolution, and includes digital correction circuitry to resolve issues from clock skew. A .18μm CMOS prototype occupies 500μm × 500μm of area, generates a 900MHz clock from a 10MHz reference, has phase noise of −90dBc/Hz at 1MHz offset and 2.62psrms jitter while consuming 4.2mA from a 1.8V supply.