{"title":"提高2T2MTJ STT-MRAM小区可靠性和带宽的自参考传感","authors":"Jang-Woo Ryu, K. Kwon","doi":"10.1109/NVMTS.2016.7781510","DOIUrl":null,"url":null,"abstract":"This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A self-reference sensing for improving reliability and bandwidth with 2T2MTJ STT-MRAM cell\",\"authors\":\"Jang-Woo Ryu, K. Kwon\",\"doi\":\"10.1109/NVMTS.2016.7781510\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.\",\"PeriodicalId\":228005,\"journal\":{\"name\":\"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)\",\"volume\":\"2019 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMTS.2016.7781510\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2016.7781510","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A self-reference sensing for improving reliability and bandwidth with 2T2MTJ STT-MRAM cell
This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.
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