{"title":"用于感应电机驱动的准谐振直流电路PWM逆变器","authors":"J.J. Jafar, B. G. Fernandes","doi":"10.1109/IAS.1999.806011","DOIUrl":null,"url":null,"abstract":"This paper presents a new quasi-resonant DC-link (QRDCL) PWM inverter with zero voltage switching (ZVS) capability. The proposed circuit creates zero voltage intervals in the DC-link to facilitate ZVS of the inverter under all loading conditions and any PWM technique can be used to control the output voltage of the inverter. The maximum voltage across the inverter device is maintained around (1.01-1.08) p.u. The paper explains the principle of operation of the circuit and describes the analysis of each mode of operation. It also gives the design criteria for achieving zero voltage switching under all loading conditions. Detailed PSPICE simulation studies are carried out to study the performance of the proposed circuit under all the possible operating conditions and these results are verified experimentally. The simulation and experimental results of this inverter feeding an induction motor drive are also given.","PeriodicalId":125787,"journal":{"name":"Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A quasi-resonant DC-link PWM inverter for induction motor drive\",\"authors\":\"J.J. Jafar, B. G. Fernandes\",\"doi\":\"10.1109/IAS.1999.806011\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new quasi-resonant DC-link (QRDCL) PWM inverter with zero voltage switching (ZVS) capability. The proposed circuit creates zero voltage intervals in the DC-link to facilitate ZVS of the inverter under all loading conditions and any PWM technique can be used to control the output voltage of the inverter. The maximum voltage across the inverter device is maintained around (1.01-1.08) p.u. The paper explains the principle of operation of the circuit and describes the analysis of each mode of operation. It also gives the design criteria for achieving zero voltage switching under all loading conditions. Detailed PSPICE simulation studies are carried out to study the performance of the proposed circuit under all the possible operating conditions and these results are verified experimentally. The simulation and experimental results of this inverter feeding an induction motor drive are also given.\",\"PeriodicalId\":125787,\"journal\":{\"name\":\"Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IAS.1999.806011\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAS.1999.806011","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A quasi-resonant DC-link PWM inverter for induction motor drive
This paper presents a new quasi-resonant DC-link (QRDCL) PWM inverter with zero voltage switching (ZVS) capability. The proposed circuit creates zero voltage intervals in the DC-link to facilitate ZVS of the inverter under all loading conditions and any PWM technique can be used to control the output voltage of the inverter. The maximum voltage across the inverter device is maintained around (1.01-1.08) p.u. The paper explains the principle of operation of the circuit and describes the analysis of each mode of operation. It also gives the design criteria for achieving zero voltage switching under all loading conditions. Detailed PSPICE simulation studies are carried out to study the performance of the proposed circuit under all the possible operating conditions and these results are verified experimentally. The simulation and experimental results of this inverter feeding an induction motor drive are also given.
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