{"title":"开关电容电路的符号故障建模","authors":"J. Cheng, G. Shi, Andy Tai, F. Lee","doi":"10.1109/TENCON.2013.6719067","DOIUrl":null,"url":null,"abstract":"A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided.","PeriodicalId":425023,"journal":{"name":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Symbolic fault modeling for switched-capacitor circuits\",\"authors\":\"J. Cheng, G. Shi, Andy Tai, F. Lee\",\"doi\":\"10.1109/TENCON.2013.6719067\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided.\",\"PeriodicalId\":425023,\"journal\":{\"name\":\"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCON.2013.6719067\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.2013.6719067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Symbolic fault modeling for switched-capacitor circuits
A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided.