使用衬底偏置的大型扇入多米诺门的泄漏控制

A. Youssef, M. Anis, M. Elmasry
{"title":"使用衬底偏置的大型扇入多米诺门的泄漏控制","authors":"A. Youssef, M. Anis, M. Elmasry","doi":"10.1109/ICM.2003.238360","DOIUrl":null,"url":null,"abstract":"Small area, Low power and high speed circuits are essential components propelling today's microprocessors. Domino logic gates are basic components in this family. One disadvantage pertaining to domino gates is the trade-off between speed and noise immunity, which is highly affected by leakage currents. In this paper, we propose the usage of reverse bulk node voltage in order to resolve this trade-off, while reducing the active leakage power consumed. A 50% reduction in active leakage power, and 40% saving in gate delay were achieved.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Leakage control for large fan-in Domino gates using substrate biasing\",\"authors\":\"A. Youssef, M. Anis, M. Elmasry\",\"doi\":\"10.1109/ICM.2003.238360\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Small area, Low power and high speed circuits are essential components propelling today's microprocessors. Domino logic gates are basic components in this family. One disadvantage pertaining to domino gates is the trade-off between speed and noise immunity, which is highly affected by leakage currents. In this paper, we propose the usage of reverse bulk node voltage in order to resolve this trade-off, while reducing the active leakage power consumed. A 50% reduction in active leakage power, and 40% saving in gate delay were achieved.\",\"PeriodicalId\":180690,\"journal\":{\"name\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2003.238360\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2003.238360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

小面积、低功耗和高速电路是推动当今微处理器发展的重要组成部分。Domino逻辑门是这个系列中的基本组件。与多米诺门有关的一个缺点是速度和噪声抗扰度之间的权衡,这受到泄漏电流的高度影响。在本文中,我们提出使用反向块节点电压来解决这种权衡,同时减少有源泄漏功率的消耗。有源泄漏功率降低50%,栅极延迟降低40%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Leakage control for large fan-in Domino gates using substrate biasing
Small area, Low power and high speed circuits are essential components propelling today's microprocessors. Domino logic gates are basic components in this family. One disadvantage pertaining to domino gates is the trade-off between speed and noise immunity, which is highly affected by leakage currents. In this paper, we propose the usage of reverse bulk node voltage in order to resolve this trade-off, while reducing the active leakage power consumed. A 50% reduction in active leakage power, and 40% saving in gate delay were achieved.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach Parasitic effect analysis for a differential LNA design Comparative energy and delay of energy recovery and square wave clock flip-flops for high-performance and low-power applications Ant colony algorithm for evolutionary design of arithmetic circuits Multifunction generator using Horner scheme and small tables
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1