On systolic mapping of multi-stage algorithms

The authors present a more general mapping problem called multi-stage systolic mapping which focuses on the computing algorithms containing more than one nested loop constructs to be executed sequentially. Since the emerged interface problem now becomes the dominant factor in performing the mapping, the authors argue that the adjacent stages should have matched interface to reduce the overhead. For this, the conditions of interface matching between two stage's mappings are established. A systematic method to derive the interface matched mapping is also presented. To improve the performance degradation due to the initial and final phases of computation in systolic computing, the inter-stage computation concurrency is explored by overlapping part of the computations in successive stages and thus effectively reduces the computation latency. With these results, the multi-stage systolic mapping tool (MSSM) is developed and several design examples are presented to illustrate the potential use of MSSM.<>