Exploring the behavior of parallel connected SiC power MOSFETs influenced by performance spread in circuit simulations

In order to investigate the performance of SiC power MOSFETs and especially their applicability for parallelization, ten samples of Cree's C2M0080120D MOSFET are investigated in terms of their electrical and thermal behavior. A significant spread of on-state resistance and threshold voltage is observed, where the maximum differences are ΔI ≈ 10 mΩ, i.e. 12.5 % at a current of 20 A, and ΔVth ≈ 1 V, respectively. The parallelization of these devices is analyzed by developing a numerically efficient and semi-physical Spice model for the given MOSFET. Circuit simulations of ten paralleled devices show a maximum imbalance in current of 13 % and a maximum imbalance in junction to case temperature of around 11 % between the devices. The turn-on losses increase by 2 % while the turn-off losses remain unchanged compared to ten parallel devices with similar, averaged on-resistance. Applying these ten parallel MOSFETs with different characteristics to a 50 kW bi-directional DC/DC converter in boost mode increases the losses by 46 W in comparison to ten identical MOSFETs with averaged characteristics.