具有恒定环路带宽的全集成48ghz低噪声锁相环

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI:10.1109/SMIC.2008.27

F. Herzel, S. Glisic, S. Osmany, J. Scheytt, K. Schmalz, W. Winkler, M. Engels

{"title":"具有恒定环路带宽的全集成48ghz低噪声锁相环","authors":"F. Herzel, S. Glisic, S. Osmany, J. Scheytt, K. Schmalz, W. Winkler, M. Engels","doi":"10.1109/SMIC.2008.27","DOIUrl":null,"url":null,"abstract":"We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"418 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth\",\"authors\":\"F. Herzel, S. Glisic, S. Osmany, J. Scheytt, K. Schmalz, W. Winkler, M. Engels\",\"doi\":\"10.1109/SMIC.2008.27\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.\",\"PeriodicalId\":350325,\"journal\":{\"name\":\"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"volume\":\"418 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMIC.2008.27\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2008.27","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

我们提出了一种用于低噪声频率合成器的双环锁相环结构。该方法在用于60 GHz无线收发器的0.25 μ SiGe BiCMOS技术的48 GHz锁相环上进行了实验验证。该设计采用两个并联电荷泵，其中一个控制回路动力学，并在最佳输出电压下偏置。这平衡了环路带宽，减少了电荷泵不匹配。

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A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.

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2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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