{"title":"误码和成帧对包延迟影响的自省","authors":"U. K. Roy","doi":"10.1109/ICCECE.2016.8009552","DOIUrl":null,"url":null,"abstract":"To deliver data in computer networks, it is often divided into smaller chunks/frames/packets (called framing) for various reasons such as regulating flow, multiplexing, switching, error control, etc. In a store-and-forward network, a carefully chosen packet-size can drastically improve network performance especially end-to-end delivery time. In this paper, we have inspected the effect of packet size and bit-error on packet delay with rigorous theoretic derivation. We have figured out that delay is a non-linear function of (i) message size, (ii) number of hops the packet traverses, (iii) bit-error rate and (iv) the number the message is divided into chunks. The first three are not customizable. However, we can carefully choose the last one to minimize delay. We devised an expression to find optimal number of packets that minimizes the delay. We have also shown how this optimal number of packets varies with number of hops, message size and bit-error. Analytical and simulation results show the correctness of the proposed scheme.","PeriodicalId":414303,"journal":{"name":"2016 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An introspection on impact of bit-error and framing on packet delay\",\"authors\":\"U. K. Roy\",\"doi\":\"10.1109/ICCECE.2016.8009552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To deliver data in computer networks, it is often divided into smaller chunks/frames/packets (called framing) for various reasons such as regulating flow, multiplexing, switching, error control, etc. In a store-and-forward network, a carefully chosen packet-size can drastically improve network performance especially end-to-end delivery time. In this paper, we have inspected the effect of packet size and bit-error on packet delay with rigorous theoretic derivation. We have figured out that delay is a non-linear function of (i) message size, (ii) number of hops the packet traverses, (iii) bit-error rate and (iv) the number the message is divided into chunks. The first three are not customizable. However, we can carefully choose the last one to minimize delay. We devised an expression to find optimal number of packets that minimizes the delay. We have also shown how this optimal number of packets varies with number of hops, message size and bit-error. Analytical and simulation results show the correctness of the proposed scheme.\",\"PeriodicalId\":414303,\"journal\":{\"name\":\"2016 International Conference on Computer, Electrical & Communication Engineering (ICCECE)\",\"volume\":\"112 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Computer, Electrical & Communication Engineering (ICCECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCECE.2016.8009552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCECE.2016.8009552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An introspection on impact of bit-error and framing on packet delay
To deliver data in computer networks, it is often divided into smaller chunks/frames/packets (called framing) for various reasons such as regulating flow, multiplexing, switching, error control, etc. In a store-and-forward network, a carefully chosen packet-size can drastically improve network performance especially end-to-end delivery time. In this paper, we have inspected the effect of packet size and bit-error on packet delay with rigorous theoretic derivation. We have figured out that delay is a non-linear function of (i) message size, (ii) number of hops the packet traverses, (iii) bit-error rate and (iv) the number the message is divided into chunks. The first three are not customizable. However, we can carefully choose the last one to minimize delay. We devised an expression to find optimal number of packets that minimizes the delay. We have also shown how this optimal number of packets varies with number of hops, message size and bit-error. Analytical and simulation results show the correctness of the proposed scheme.