一个16位自测试倍增器

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468773

J. Rainard, Y. Vernay

{"title":"一个16位自测试倍增器","authors":"J. Rainard, Y. Vernay","doi":"10.1109/ESSCIRC.1980.5468773","DOIUrl":null,"url":null,"abstract":"A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 16 Bit Self-Testing Multiplier\",\"authors\":\"J. Rainard, Y. Vernay\",\"doi\":\"10.1109/ESSCIRC.1980.5468773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

一个单芯片集成乘法器，工作在16位字上，有两种不同的工作模式(串行或并行)，并能够通过内部监控系统(约25%的额外硅面积)发出任何故障信号。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 16 Bit Self-Testing Multiplier

A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

自引率

0.00%

发文量

期刊最新文献

Chip Design in an Advanced CMOS Technology High Speed High Density Poly I2L Subscribers' Connection Units (S.C.U.) PER-Channel CODEC/Filter A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM