{"title":"利用并行测试结构加速14nm器件学习和良率斜坡，作为新的在线参数测试策略的一部分","authors":"Garry Moore, J. Liao, Scott McDade, B. Verzi","doi":"10.1109/ICMTS.2015.7106106","DOIUrl":null,"url":null,"abstract":"This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy\",\"authors\":\"Garry Moore, J. Liao, Scott McDade, B. Verzi\",\"doi\":\"10.1109/ICMTS.2015.7106106\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.\",\"PeriodicalId\":177627,\"journal\":{\"name\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2015.7106106\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy
This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.
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