{"title":"一个110 db动态范围,76 db峰值信噪比压缩音频应用连续时间调制器","authors":"Saravana Kumar, S. Chatterjee","doi":"10.1109/VLSID.2012.45","DOIUrl":null,"url":null,"abstract":"This paper presents a companding continuous-time ΔΣ ADC for audio applications. The 3rd-order modulator uses a 3-bit companding quantizer and has an over sampling rate of 64. The companding quantizer is implemented by a log amplifier followed by a flash ADC. The modulator, in simulation, achieves a peak signal-to-noise ratio of 76 dB, a dynamic range of 110 dB in a 24 kHz bandwidth and dissipates 860 μW of power.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications\",\"authors\":\"Saravana Kumar, S. Chatterjee\",\"doi\":\"10.1109/VLSID.2012.45\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a companding continuous-time ΔΣ ADC for audio applications. The 3rd-order modulator uses a 3-bit companding quantizer and has an over sampling rate of 64. The companding quantizer is implemented by a log amplifier followed by a flash ADC. The modulator, in simulation, achieves a peak signal-to-noise ratio of 76 dB, a dynamic range of 110 dB in a 24 kHz bandwidth and dissipates 860 μW of power.\",\"PeriodicalId\":405021,\"journal\":{\"name\":\"2012 25th International Conference on VLSI Design\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 25th International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2012.45\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications
This paper presents a companding continuous-time ΔΣ ADC for audio applications. The 3rd-order modulator uses a 3-bit companding quantizer and has an over sampling rate of 64. The companding quantizer is implemented by a log amplifier followed by a flash ADC. The modulator, in simulation, achieves a peak signal-to-noise ratio of 76 dB, a dynamic range of 110 dB in a 24 kHz bandwidth and dissipates 860 μW of power.