Chen Huang, Liang Zhou, H. Wen, Qian Zhao, Feng Xu
{"title":"采用固定误差模式，降低LDPC的误差层","authors":"Chen Huang, Liang Zhou, H. Wen, Qian Zhao, Feng Xu","doi":"10.1109/ICEIT.2010.5608383","DOIUrl":null,"url":null,"abstract":"This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern. The simulation results have demonst-rated the performance of the novel scheme is efficient. The error floor that we estimate is below 1e-15. This approach can be used on the high speed 100Gp/s communication.","PeriodicalId":346498,"journal":{"name":"2010 International Conference on Educational and Information Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Lower the error floor of LDPC with fixed error pattern\",\"authors\":\"Chen Huang, Liang Zhou, H. Wen, Qian Zhao, Feng Xu\",\"doi\":\"10.1109/ICEIT.2010.5608383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern. The simulation results have demonst-rated the performance of the novel scheme is efficient. The error floor that we estimate is below 1e-15. This approach can be used on the high speed 100Gp/s communication.\",\"PeriodicalId\":346498,\"journal\":{\"name\":\"2010 International Conference on Educational and Information Technology\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Educational and Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEIT.2010.5608383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Educational and Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEIT.2010.5608383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Lower the error floor of LDPC with fixed error pattern
This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern. The simulation results have demonst-rated the performance of the novel scheme is efficient. The error floor that we estimate is below 1e-15. This approach can be used on the high speed 100Gp/s communication.
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