Purely-digital versus mixed-signal self-calibration techniques in high-resolution pipeline ADCs

This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as the ideal conversion characteristic of this stage is known. A novel Gaussian Noise Generator is used as the input analog stimulus and, on the digital side, the calibration algorithm does not require explicit multiplications, which greatly simplifies the digital circuitry. Experimental measurements of a 13-bit ADC fabricated in 90 nm CMOS, after calibration and at 40 MS/s, show that the SFDR is improved by over 14 dB (to 84 dB), the THD is improved by over 10 dB (to −80 dB), achieving a peak ENOB of 11.3 bits for a 10 MHz input and with a 1.2 V power supply.