A novel technique of leakage power reduction in 9T SRAM design in FinFET technology

Power consumption has become hurdle for recent IC design as technology scale down below 45nm. Aggressive nanoscaling of MOS transistor in process technology has advanced in chip density, but to achieve high performance and lower power consumption by continues scaling results in shorter channel effect and Lowering of Drain Induced Barrier Lowering (DIBL). To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper we have utilize the property of FinFET technology in SRAM circuit design to lower power consumption. Proposed circuit shows maximum saving of dynamic power up to 76.57% in 4T, maximum leakage power saving up to 53.21% in 6T at 25°C and 45.13% at 110°C. All simulation is performed using HSPICE simulator by using Berkley Productive Technology model (BPTM) at 32nm.