Boundary scan design and verification flow using buffer chain method

Boundary scan is a well-known standard DFT technique, called IEEE Std 1149.1, that is designed with boundary scan registers placed between pads and internal logic. In this paper we propose a boundary scan design and verification flow using a buffer chain method. The advantages of the proposed flow include: (1) the buffer chain method is easy to implement using the Samsung in-house tool; (2) the flow is effective in solving the post-layout problems at the pre-layout step; and (3) the flow reduces the TAT (Turn Around Time) of the boundary scan design and verification.