T. Ohbu, K. Kodani, N. Tada, T. Matsumoto, K. Kijima, S. Saito
{"title":"电源模块封装结构研究","authors":"T. Ohbu, K. Kodani, N. Tada, T. Matsumoto, K. Kijima, S. Saito","doi":"10.1109/IWIPP.2000.885180","DOIUrl":null,"url":null,"abstract":"In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Study of power module package structures\",\"authors\":\"T. Ohbu, K. Kodani, N. Tada, T. Matsumoto, K. Kijima, S. Saito\",\"doi\":\"10.1109/IWIPP.2000.885180\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible.\",\"PeriodicalId\":359131,\"journal\":{\"name\":\"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-07-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWIPP.2000.885180\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWIPP.2000.885180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible.
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