Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885189
E. McShane, K. Shenai
Device avalanche rating is a common figure of merit for comparing packaged parts. The rating has been shown to be affected by internal thermal dynamics. These dynamics can be influenced by the package thermal properties. The effect of package thermal performance on avalanche rating is investigated and a compact analytical expression to obtain the avalanche current is described.
{"title":"Package effects on avalanche rating of power MOSFETs","authors":"E. McShane, K. Shenai","doi":"10.1109/IWIPP.2000.885189","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885189","url":null,"abstract":"Device avalanche rating is a common figure of merit for comparing packaged parts. The rating has been shown to be affected by internal thermal dynamics. These dynamics can be influenced by the package thermal properties. The effect of package thermal performance on avalanche rating is investigated and a compact analytical expression to obtain the avalanche current is described.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133904953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885177
P. Singh, S. Mazzuca, Y. Yao, G. Galyon, V. Ronken, L. Hedlund, J. Kinnard
The trend to pack more power in smaller spaces is leading to higher rates of computer power supply arcing in the field. Power density increase is being achieved by decreasing the spacing between features such as the power train MOSFET leads and by increasing the switching frequency. Both of these changes make power supplies more prone to field arcing. This paper discloses a technique called the partial vacuum test to predict the arcing propensity in power supplies. The partial vacuum test also helps determine the corrective actions needed to avoid field arcing by indicating the locations susceptible to arcing. The paper also describes a test called the zinc spray test that can help determine the minimum spacing between features, subjected to high voltages with high frequency harmonics, that will not arc in the field.
{"title":"Power supply arcing","authors":"P. Singh, S. Mazzuca, Y. Yao, G. Galyon, V. Ronken, L. Hedlund, J. Kinnard","doi":"10.1109/IWIPP.2000.885177","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885177","url":null,"abstract":"The trend to pack more power in smaller spaces is leading to higher rates of computer power supply arcing in the field. Power density increase is being achieved by decreasing the spacing between features such as the power train MOSFET leads and by increasing the switching frequency. Both of these changes make power supplies more prone to field arcing. This paper discloses a technique called the partial vacuum test to predict the arcing propensity in power supplies. The partial vacuum test also helps determine the corrective actions needed to avoid field arcing by indicating the locations susceptible to arcing. The paper also describes a test called the zinc spray test that can help determine the minimum spacing between features, subjected to high voltages with high frequency harmonics, that will not arc in the field.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"32 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885182
E. McShane, K. Shenai
The performance of RF power MOSFETs in amplifier applications is often critically determined by the values of package and device parasitic reactive elements. These elements are frequently characterized using special "open-package" or "golden" reference units. Repetitive or multiple measurements may also be required. In this paper, methods for de-embedding package inductances and extracting device capacitances are presented. Using the presented methodology, the gate, drain, and source inductances, as well as the input capacitance, are obtained from two simple S-parameter measurements. Similar simple AC measurements are used to obtain the output and reverse-transfer capacitances. Inductance is measured under zero-current conditions, but capacitances are extracted with and without current flowing. The methodology can be performed on any packaged device and does not require a precisely characterized reference unit. Results are presented and demonstrated by comparison with reported data sheet values and with finite-element numerical simulation results.
{"title":"RF de-embedding technique for extracting power MOSFET package parasitics","authors":"E. McShane, K. Shenai","doi":"10.1109/IWIPP.2000.885182","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885182","url":null,"abstract":"The performance of RF power MOSFETs in amplifier applications is often critically determined by the values of package and device parasitic reactive elements. These elements are frequently characterized using special \"open-package\" or \"golden\" reference units. Repetitive or multiple measurements may also be required. In this paper, methods for de-embedding package inductances and extracting device capacitances are presented. Using the presented methodology, the gate, drain, and source inductances, as well as the input capacitance, are obtained from two simple S-parameter measurements. Similar simple AC measurements are used to obtain the output and reverse-transfer capacitances. Inductance is measured under zero-current conditions, but capacitances are extracted with and without current flowing. The methodology can be performed on any packaged device and does not require a precisely characterized reference unit. Results are presented and demonstrated by comparison with reported data sheet values and with finite-element numerical simulation results.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885175
W. J. Sarjeant, D.T. Staffiere
Implications of advances in capacitor technology, and their relations to power electronics is the result of several years of meetings, reviews, idea exchanges, philosophical discussion, agreements, and occasional controversy. At a deeper level, it represents findings and conclusions of career-long studies by those knowledgeable in the capacitor field. This paper reports on the implications of recent technology advances, especially in high frequency graceful aging new multiple layer polymer technologies, enabling the gigahertz power electronics of the future. The study was conducted under the auspices of the Power Sources Manufacturer's Association (PSMA) in order to encourage wide and unrestricted dialogue among manufacturers, developers, and users of capacitors. The body of technology represented in the report suggests the formation of a forum for ongoing discussions on the state and future of the art.
{"title":"A report on packaging implications of advances in capacitor technologies","authors":"W. J. Sarjeant, D.T. Staffiere","doi":"10.1109/IWIPP.2000.885175","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885175","url":null,"abstract":"Implications of advances in capacitor technology, and their relations to power electronics is the result of several years of meetings, reviews, idea exchanges, philosophical discussion, agreements, and occasional controversy. At a deeper level, it represents findings and conclusions of career-long studies by those knowledgeable in the capacitor field. This paper reports on the implications of recent technology advances, especially in high frequency graceful aging new multiple layer polymer technologies, enabling the gigahertz power electronics of the future. The study was conducted under the auspices of the Power Sources Manufacturer's Association (PSMA) in order to encourage wide and unrestricted dialogue among manufacturers, developers, and users of capacitors. The body of technology represented in the report suggests the formation of a forum for ongoing discussions on the state and future of the art.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123115033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885190
J. Strydom, J. D. van Wyk, J. Ferreira
The integrated planar resonant/transformer structure analysed is constructed from planar ferrites, conductive layers, leakage layers and slabs of ceramic dielectric. The electromagnetic limits are analysed in terms of the permeabilities, permittivities and conductivities, skin effect, breakdown field and physical dimensions. An example of a converter with an integrated resonant/transformer (LLCT) structure is used to illustrate the analysis. This analysis indicates that the electromagnetic limits results in volumes two orders of magnitude smaller than at present, illustrating that the power density is currently only limited by construction technology. The thermal limit is expected to be the next barrier within one order of magnitude.
{"title":"Electromagnetic limits of planar integrated resonant/transformer structures for power electronic applications","authors":"J. Strydom, J. D. van Wyk, J. Ferreira","doi":"10.1109/IWIPP.2000.885190","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885190","url":null,"abstract":"The integrated planar resonant/transformer structure analysed is constructed from planar ferrites, conductive layers, leakage layers and slabs of ceramic dielectric. The electromagnetic limits are analysed in terms of the permeabilities, permittivities and conductivities, skin effect, breakdown field and physical dimensions. An example of a converter with an integrated resonant/transformer (LLCT) structure is used to illustrate the analysis. This analysis indicates that the electromagnetic limits results in volumes two orders of magnitude smaller than at present, illustrating that the power density is currently only limited by construction technology. The thermal limit is expected to be the next barrier within one order of magnitude.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885185
Xingsheng Liu, Xiukuan Jing, G. Lu
Through a comparative study of wire bonding and solder bumping of power semiconductor devices, the advantages of solder bump interconnection are indicated. The fabrication process, electrical performance, thermal performance and reliability issues and results are presented and compared for these two technologies.
{"title":"A comparative study of wire bonding versus solder bumping of power semiconductor devices","authors":"Xingsheng Liu, Xiukuan Jing, G. Lu","doi":"10.1109/IWIPP.2000.885185","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885185","url":null,"abstract":"Through a comparative study of wire bonding and solder bumping of power semiconductor devices, the advantages of solder bump interconnection are indicated. The fabrication process, electrical performance, thermal performance and reliability issues and results are presented and compared for these two technologies.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123733381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885172
M. Trivedi, K. Shenai
This paper describes the characterization of the performance of a 100 V/1 A SiC p-n diode and a 50 V/0.5 A SiC JFET in a DC-DC buck converter. A fundamental study of material defects and process techniques in SiC is needed for significant material purification. The nonidealities of device operation are clearly indicated, and the impact on buck converter operation is described. Improved device design and fabrication techniques are required for further improvement in device performance.
本文描述了用于DC-DC降压变换器的100 V/1 a SiC p-n二极管和50 V/0.5 a SiC JFET的性能表征。SiC材料缺陷和工艺技术的基础研究是实现材料净化的重要手段。明确指出了器件运行的非理想性，并描述了其对降压变换器运行的影响。为了进一步提高器件性能，需要改进器件设计和制造技术。
{"title":"Performance of silicon carbide devices in power converters","authors":"M. Trivedi, K. Shenai","doi":"10.1109/IWIPP.2000.885172","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885172","url":null,"abstract":"This paper describes the characterization of the performance of a 100 V/1 A SiC p-n diode and a 50 V/0.5 A SiC JFET in a DC-DC buck converter. A fundamental study of material defects and process techniques in SiC is needed for significant material purification. The nonidealities of device operation are clearly indicated, and the impact on buck converter operation is described. Improved device design and fabrication techniques are required for further improvement in device performance.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125300928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885180
T. Ohbu, K. Kodani, N. Tada, T. Matsumoto, K. Kijima, S. Saito
In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible.
{"title":"Study of power module package structures","authors":"T. Ohbu, K. Kodani, N. Tada, T. Matsumoto, K. Kijima, S. Saito","doi":"10.1109/IWIPP.2000.885180","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885180","url":null,"abstract":"In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127052068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885110
J. Flannery, P. Cheasty, M. Meinhardt, M. Ludwig, P. McCloskey, C. O'Mathúna
This paper presents the results of a detailed benchmarking of the status of power packaging of DC/DC converters in the 100 W range. This work was carried out as part of the StatPEP project which was co-sponsored by the PSMA and PEI Technologies. This benchmarking has established the present best practice in the power electronic packaging of DC/DC power converters currently being manufactured. Ten DC/DC power supplies were identified. The units included two from government and space applications, seven telecom units and one common industrial unit. The main specifications of these supplies are rated power of /spl sim/100 W, input voltage of 48 V and single output voltage (V/sub o/) as low as possible in the range 5 V to 2 V. Electrical and thermal properties were measured to confirm individual data sheet specifications. The investigation comprised an analysis of the physical structure of converters, the nature of external packaging, the type of base plates, substrates and potting compounds used as well as the converter's power/energy/current densities. Also addressed was the interconnect between circuit components, the assembly technology used, overall numbers of components and solder joints and magnetic components (packaging type, technology, level of integration), Of particular interest in the benchmarking process is an analysis of how packaging is used to address thermal and current density issues as well as the identification of suitable figures of merit to quantify the status of power packaging and allow progress to be monitored over time.
{"title":"Present practice of power packaging for DC/DC converters","authors":"J. Flannery, P. Cheasty, M. Meinhardt, M. Ludwig, P. McCloskey, C. O'Mathúna","doi":"10.1109/IWIPP.2000.885110","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885110","url":null,"abstract":"This paper presents the results of a detailed benchmarking of the status of power packaging of DC/DC converters in the 100 W range. This work was carried out as part of the StatPEP project which was co-sponsored by the PSMA and PEI Technologies. This benchmarking has established the present best practice in the power electronic packaging of DC/DC power converters currently being manufactured. Ten DC/DC power supplies were identified. The units included two from government and space applications, seven telecom units and one common industrial unit. The main specifications of these supplies are rated power of /spl sim/100 W, input voltage of 48 V and single output voltage (V/sub o/) as low as possible in the range 5 V to 2 V. Electrical and thermal properties were measured to confirm individual data sheet specifications. The investigation comprised an analysis of the physical structure of converters, the nature of external packaging, the type of base plates, substrates and potting compounds used as well as the converter's power/energy/current densities. Also addressed was the interconnect between circuit components, the assembly technology used, overall numbers of components and solder joints and magnetic components (packaging type, technology, level of integration), Of particular interest in the benchmarking process is an analysis of how packaging is used to address thermal and current density issues as well as the identification of suitable figures of merit to quantify the status of power packaging and allow progress to be monitored over time.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885181
M. Rencz, V. Székely, A. Poppe, B. Courtois
Thermal simulation is a frequently needed task in the design of integrated power packaging. Thermal simulation is used in the design of new devices, in the design of the placement of the dissipating elements on the chip and for the design of the packages. Thermal simulators can help to find the best mounting solutions for the devices if they have to operate in thermally strained conditions. Thermal simulation is usually done using finite element method (FEM) based simulator programs. These are general-purpose expensive simulators, where the general usability comes together with complicated, and usually difficult to learn and difficult to use user interfaces, and these programs are relatively slow and inaccurate. To overcome these problems, we have developed two fast and easy to use 2D and 3D thermal simulator programs, SUNRED (Szekely and Rencz, 1998) and THERMAN (Csendes et al, 1998; Szekely et al, 1999). In the recent development, the first goal was to create user friendly tools which design engineers are happy to use in thermal design tasks, since the tools are fast enough to provide answers to their thermal questions almost immediately. As a result of this feature, the designers can study the effects on the thermal behavior of all modifications in the geometry of their structure or in the boundary conditions immediately on their computer screen.
热仿真是集成电源封装设计中经常需要进行的工作。热模拟用于新器件的设计，芯片上散热元件的放置设计以及封装的设计。如果设备必须在热应变条件下运行，热模拟器可以帮助找到最佳的安装解决方案。热模拟通常使用基于有限元法(FEM)的模拟器程序进行。这些是通用的昂贵的模拟器，其中一般的可用性与复杂的，通常难以学习和难以使用的用户界面，这些程序是相对缓慢和不准确的。为了克服这些问题，我们开发了两个快速且易于使用的2D和3D热模拟器程序，SUNRED (Szekely和Rencz, 1998)和THERMAN (Csendes等人，1998;Szekely et al, 1999)。在最近的开发中，第一个目标是创建用户友好的工具，设计工程师乐于在热设计任务中使用这些工具，因为这些工具足够快，几乎可以立即为他们的热问题提供答案。由于这一特点，设计人员可以立即在计算机屏幕上研究其结构几何形状或边界条件的所有修改对热行为的影响。
{"title":"Friendly tools for the thermal simulation of power packages","authors":"M. Rencz, V. Székely, A. Poppe, B. Courtois","doi":"10.1109/IWIPP.2000.885181","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885181","url":null,"abstract":"Thermal simulation is a frequently needed task in the design of integrated power packaging. Thermal simulation is used in the design of new devices, in the design of the placement of the dissipating elements on the chip and for the design of the packages. Thermal simulators can help to find the best mounting solutions for the devices if they have to operate in thermally strained conditions. Thermal simulation is usually done using finite element method (FEM) based simulator programs. These are general-purpose expensive simulators, where the general usability comes together with complicated, and usually difficult to learn and difficult to use user interfaces, and these programs are relatively slow and inaccurate. To overcome these problems, we have developed two fast and easy to use 2D and 3D thermal simulator programs, SUNRED (Szekely and Rencz, 1998) and THERMAN (Csendes et al, 1998; Szekely et al, 1999). In the recent development, the first goal was to create user friendly tools which design engineers are happy to use in thermal design tasks, since the tools are fast enough to provide answers to their thermal questions almost immediately. As a result of this feature, the designers can study the effects on the thermal behavior of all modifications in the geometry of their structure or in the boundary conditions immediately on their computer screen.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"88 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133350994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：