一个基于标准单元的全数字时间-数字转换器，具有可重构的分辨率和在线背景校准

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI:10.1109/ESSCIRC.2011.6044960

Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx

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引用次数: 8

摘要

本文提出了一种基于标准单元的全数字时间-数字转换器，具有可重构分辨率，达到子门延迟。采用自动化的数字化设计流程实现了基于空间过采样的结构。它具有强大的在线背景校准方案，用于增益跟踪。90nm原型芯片在0.26 mm2的面积上，消耗[1-8]mA，达到[39-14]ps的有效分辨率

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A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration

This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39–14] ps effective resolution consuming [1–8] mA, in an area of only 0.26 mm2

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2011 Proceedings of the ESSCIRC (ESSCIRC)

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