R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge
{"title":"一种18K双极动态随机存取存储器芯片","authors":"R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge","doi":"10.1109/ESSCIRC.1980.5468765","DOIUrl":null,"url":null,"abstract":"A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An 18K Bipolar Dynamic Random Access Memory Chip\",\"authors\":\"R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge\",\"doi\":\"10.1109/ESSCIRC.1980.5468765\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468765\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.
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