基于65nm SOI CMOS的6.7 enob、500 ms /s、5.1 mw动态流水线ADC

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI:10.1109/ESSCIRC.2011.6044981

R. Nguyen, C. Raynaud, A. Cathelin, B. Murmann

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引用次数: 4

摘要

采用不完全瞬态稳定的低功率电荷泵式动态增益级实现了一个6.7 enob、500 ms /s的流水线ADC。该实验转换器在65nm SOI CMOS中占据0.02 mm2的有源面积，在1.2 v电源下耗散5.1 mW。它在Nyquist附近的输入实现了41.5 dB的SNDR，对应于98 fJ/ conv.step的优值。

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A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS

A 6.7-ENOB, 500-MS/s pipeline ADC is realized using low-power charge pump-like dynamic gain stages operating with incomplete transient settling. The experimental converter occupies an active area of 0.02 mm2 in 65-nm SOI CMOS and dissipates 5.1 mW from a 1.2-V supply. It achieves an SNDR of 41.5 dB for inputs near Nyquist, corresponding to a figure of merit of 98 fJ/conv.-step.

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2011 Proceedings of the ESSCIRC (ESSCIRC)

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