{"title":"集成LDMOS功率器件中布局相关金属电阻的物理紧凑建模","authors":"M.L. Kniffin, R. Thoma, J. Victory","doi":"10.1109/ISPSD.2000.856799","DOIUrl":null,"url":null,"abstract":"Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices\",\"authors\":\"M.L. Kniffin, R. Thoma, J. Victory\",\"doi\":\"10.1109/ISPSD.2000.856799\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements.\",\"PeriodicalId\":260241,\"journal\":{\"name\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2000.856799\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices
Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements.
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