Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications

Recent advances in mobile computing and multimedia applications demand high - performance and low - power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high - performance applications. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high performance applications. The FIR filter performs the weighted summations of input sequences and is widely used in video convolution functions, signal preconditioning, and various communication applications. Recently, due to the high - performance requirement and increasing complexity of DSP and multimedia communication application. In this work, , FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime.