Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction

The increasing importance of Multiple Cell Upsets (MCU) in memories has led to the development of error correction codes that can correct multiple bit errors on nearby bits. In particular, 3-bit burst error correction codes have been recently proposed for memories with data words of up to 64 bits. In some cases, like caches, widths can be much larger than 64 bits and therefore, to protect them 3-bit burst codes with larger block sizes are needed. Most of the 3-bit burst codes presented so far are generated with a computer search program. This approach does not scale well to large word sizes. Recently an algorithmic construction has also been proposed for 3-bit burst codes that supports large word sizes. A decoding algorithm was also proposed but no implementation was provided. This paper studies the implementation of 3-bit burst error correction for large word sizes using the recently proposed algorithmic code construction. To that end, the decoding has been implemented using the algorithm proposed for those codes and a traditional syndrome decoding and both have been compared to a SEC-DED code. The results show that syndrome decoding is more efficient than the ad-hoc algorithm. Compared to a SEC-DED decoder, implementing 3-bit burst correction decoder requires approximately an increase of 2x in area, 3x in power and 20–30% in delay for word sizes of 128, 256 and 512 bits. Therefore, the impact is significant even when using the most efficient decoder implementation.