{"title":"用于便携式SoC处理器的低杂散14.4mW 1.8GHz CMOS fvc时钟发生器","authors":"Gil-Su Kim, Chulwoo Kim, Soo-Won Kim","doi":"10.1109/ASSCC.2007.4425692","DOIUrl":null,"url":null,"abstract":"A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors\",\"authors\":\"Gil-Su Kim, Chulwoo Kim, Soo-Won Kim\",\"doi\":\"10.1109/ASSCC.2007.4425692\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425692\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
基于频率电压转换器(FVC)的60 MHz至1.8 GHz时钟发生器采用0.18 μ m CMOS工艺制造,用于便携式SoC处理器。时钟发生器采用FVC和VCO同时降低功率和抖动,在1.8 V电源下实现了-54.1 dBc的杂散音、1.497 ps的有效值抖动和14.4 mW的峰对峰抖动。
A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors
A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.