采用高数据访问重用的低功耗运动估计VLSI架构

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824053

Bo-Sung Kim, Jun-Dong Cho

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引用次数: 6

摘要

本文提出了一种新的MPEG-2运动估计的VLSI结构。以前已经提出了各种全搜索块匹配算法(BMA)和基于收缩阵列的运动估计架构。然而，这些体系结构具有大量的外部内存访问效率低下。我们的新架构有效地重用数据，减少外部内存访问，并通过使用并行算法节省计算时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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VLSI architecture for low power motion estimation using high data access reuse

This paper presents a new VLSI architecture of the motion estimation in MPEG-2. Previously various full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have inefficiently a large number of external memory access. Our new architecture efficiently reuses data to decrease external memory accesses and saves the computational time by using a parallel algorithm.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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