面向人工智能应用的低功耗高速8位CMOS电流转向DAC设计

B. Krishna, S. S. Gill, Amod Kumar
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摘要

本文描述了一种用于人工智能网络中低功耗和高速辅助的当前转向8位DAC架构。该设计最适合5G和下一代高速片上通信系统(soc)。该DAC保持恒定的负载电流,从而在宽带便携式设备应用中实现更快的操作。该设计基于通过电流镜的加权电流传输,其中电流从MSB不断减小到LSB。通过选择低电流的LSB,降低了功耗。功率和面积也减少了使用2位二进制温度计解码器。DAC的积分非线性(INL)和微分非线性(DNL)分别在0.4和0.9 LSB以内。DAC的最高工作速度为1GHz,功耗约为24.2 mW,电源电压为1.8v,采用180nm CMOS技术。
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Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications
This paper describes a current steering 8-bit DAC architecture for low power and high-speed assistance in AI networks. This design is most suitable for 5G and next-generation high-speed communication systems on chip (SoCs). This DAC keeps a constant load current and leads to faster operations in wideband portable device applications. The design is based on weighted current transmission through current mirrors wherein current reduces from MSB to LSB continuously. By choosing a low current for LSB, the power dissipation reduces. Power and area are also reduced by using a 2-bit binary to thermometer decoder. The DAC's integral nonlinearity (INL) and differential nonlinearity (DNL) are found to be within 0.4 and 0.9 LSB, respectively. The DAC's highest operating speed is 1GHz, with a power dissipation of around 24.2 mW with the supply voltage of 1.8v using 180nm CMOS technology.
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