一种基于签名的规则提取方法

S. Arikati, R. Varadarajan
{"title":"一种基于签名的规则提取方法","authors":"S. Arikati, R. Varadarajan","doi":"10.1109/ICCAD.1997.643592","DOIUrl":null,"url":null,"abstract":"Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"A signature based approach to regularity extraction\",\"authors\":\"S. Arikati, R. Varadarajan\",\"doi\":\"10.1109/ICCAD.1997.643592\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.\",\"PeriodicalId\":187521,\"journal\":{\"name\":\"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1997.643592\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1997.643592","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35

摘要

规则提取是数据路径控制电路设计流程中的重要步骤。本文提出了一种从网表中自动提取规则结构的新方法。该方法足够通用,可以处理两种类型的设计:具有结构化集群信息的设计,用于在HDL级别识别的部分数据路径组件;以及没有这种结构化集群信息的设计。该方法分析电路的连通性,并使用基于签名的方法来识别规则性。
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A signature based approach to regularity extraction
Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.
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