S. Druen, M. Streibl, K. Esmark, K. Domanski, J. Niemesheim, H. Gossner, D. Schmitt-Landsiedel
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引用次数: 1
摘要
在0.13 um CMOS技术中，采用多终端TLP测量技术，在典型的I/O单元帧中访问ESD期间的电流和电压分布。该程序扩展了传统的基于ESD验证和鉴定测试的I/O库测试芯片，允许校准ESD芯片级仿真工具，并推导出精确的I/O库应用规则。
Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations
A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.
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