{"title":"一种快速瞬态无电容低差调节器","authors":"J. Qu, C. Wu","doi":"10.1117/12.2682561","DOIUrl":null,"url":null,"abstract":"As a basic module of integrated circuits, LDO is widely used in digital-to-analog and analog-to-digital conversion circuits. Based on the requirements of these circuits for power management chips, a fast-transient capacitorless low dropout regulator is proposed in this paper. To enhance the transient response, a push-pull buffer is added between the error amplifier and the power transistor. In addition, a transient enhancement circuit is used to effectively suppress the undershoot voltage and overshoot voltage and reduce the recovery time. The capacitorless LDO is verified in TSMC 180nm CMOS process. The simulation results show that when the load current changes from 1mA to 100mA within 1us, the output undershoot voltage is 83mV, and the recovery time is 1.5us; When the load current changes from 100mA to 1mA within 1us, the output overshoot voltage is 80mV and the recovery time is 1.7us. The power supply rejection of the whole system is -60dB at 1kHz and can still reach -17dB at 1MHz.","PeriodicalId":440430,"journal":{"name":"International Conference on Electronic Technology and Information Science","volume":"320 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fast-transient capacitorless low dropout regulator\",\"authors\":\"J. Qu, C. Wu\",\"doi\":\"10.1117/12.2682561\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As a basic module of integrated circuits, LDO is widely used in digital-to-analog and analog-to-digital conversion circuits. Based on the requirements of these circuits for power management chips, a fast-transient capacitorless low dropout regulator is proposed in this paper. To enhance the transient response, a push-pull buffer is added between the error amplifier and the power transistor. In addition, a transient enhancement circuit is used to effectively suppress the undershoot voltage and overshoot voltage and reduce the recovery time. The capacitorless LDO is verified in TSMC 180nm CMOS process. The simulation results show that when the load current changes from 1mA to 100mA within 1us, the output undershoot voltage is 83mV, and the recovery time is 1.5us; When the load current changes from 100mA to 1mA within 1us, the output overshoot voltage is 80mV and the recovery time is 1.7us. The power supply rejection of the whole system is -60dB at 1kHz and can still reach -17dB at 1MHz.\",\"PeriodicalId\":440430,\"journal\":{\"name\":\"International Conference on Electronic Technology and Information Science\",\"volume\":\"320 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Electronic Technology and Information Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1117/12.2682561\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Electronic Technology and Information Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2682561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast-transient capacitorless low dropout regulator
As a basic module of integrated circuits, LDO is widely used in digital-to-analog and analog-to-digital conversion circuits. Based on the requirements of these circuits for power management chips, a fast-transient capacitorless low dropout regulator is proposed in this paper. To enhance the transient response, a push-pull buffer is added between the error amplifier and the power transistor. In addition, a transient enhancement circuit is used to effectively suppress the undershoot voltage and overshoot voltage and reduce the recovery time. The capacitorless LDO is verified in TSMC 180nm CMOS process. The simulation results show that when the load current changes from 1mA to 100mA within 1us, the output undershoot voltage is 83mV, and the recovery time is 1.5us; When the load current changes from 100mA to 1mA within 1us, the output overshoot voltage is 80mV and the recovery time is 1.7us. The power supply rejection of the whole system is -60dB at 1kHz and can still reach -17dB at 1MHz.
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