一种新的容噪动态逻辑电路设计

2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI:10.1109/RME.2007.4401855

F. Frustaci, P. Corsonello, G. Cocorullo

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引用次数: 27

摘要

本文提出了一种新的耐噪声动态电路设计方法。它与以前发表的方案进行了广泛的比较。新设计可以达到以前的方案无法达到的噪声鲁棒性水平。此外，它具有最小的延迟和能量损失。在相同的能量延迟积下，与现有方案相比，该设计的噪声鲁棒性提高了116%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new noise-tolerant dynamic logic circuit design

This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.

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2007 Ph.D Research in Microelectronics and Electronics Conference

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