基于UVM的ABCStar测试平台研究

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-08-15 DOI:10.1109/RTC.2016.7543181

Li-bo Cheng, F. Anghinolfi, Ke Wang, Hong-Bo Zhu, W. Lu, Zhen-an Liu

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引用次数: 3

摘要

由于物理学家希望将越来越多的功能和算法放入前端asic中，因此(某些asic)的逻辑设计变得越来越复杂。一个可靠、健壮的功能验证试验台是集成电路设计的重要组成部分之一。本文提出了基于通用验证方法(UVM)研究的ATLAS二期升级型硅条探测器前端读出芯片测试平台。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A testbench research based on UVM for ABCStar

As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.

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2016 IEEE-NPSS Real Time Conference (RT)

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