{"title":"椭圆曲线密码系统的扫描攻击","authors":"Subidh Ali, O. Sinanoglu","doi":"10.1109/DFT.2015.7315146","DOIUrl":null,"url":null,"abstract":"We present a new scan attack on hardware implementation of Elliptic Curve Cryptography (ECC), a representative public key cipher. The existing scan attacks on ECC exploit the Design for Testability (DfT) infrastructure of the implementation to identify the internal registers used in the scalar multiplication, and leak the secret key based on a bit-flip analysis in the scalar multiplication registers. These attacks assume two internal registers are affected by the secret key in the ECC. In practical implementations, multiple internal registers are affected by the secret key, significantly complicating the identification of the targeted registers. Furthermore, existing scan attacks rely on a switch from normal to test mode, fail against the widely utilized mode-reset countermeasure. The proposed attack identifies the internal registers in a depth-first search fashion, where registers corresponding to the innermost module of the hardware design are identified first. This attack identifies all the registers related to the secret key, and does so by remaining only in the test mode, thus overcoming both limitations of the existing scan attacks.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Scan attack on Elliptic Curve Cryptosystem\",\"authors\":\"Subidh Ali, O. Sinanoglu\",\"doi\":\"10.1109/DFT.2015.7315146\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a new scan attack on hardware implementation of Elliptic Curve Cryptography (ECC), a representative public key cipher. The existing scan attacks on ECC exploit the Design for Testability (DfT) infrastructure of the implementation to identify the internal registers used in the scalar multiplication, and leak the secret key based on a bit-flip analysis in the scalar multiplication registers. These attacks assume two internal registers are affected by the secret key in the ECC. In practical implementations, multiple internal registers are affected by the secret key, significantly complicating the identification of the targeted registers. Furthermore, existing scan attacks rely on a switch from normal to test mode, fail against the widely utilized mode-reset countermeasure. The proposed attack identifies the internal registers in a depth-first search fashion, where registers corresponding to the innermost module of the hardware design are identified first. This attack identifies all the registers related to the secret key, and does so by remaining only in the test mode, thus overcoming both limitations of the existing scan attacks.\",\"PeriodicalId\":383972,\"journal\":{\"name\":\"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2015.7315146\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2015.7315146","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present a new scan attack on hardware implementation of Elliptic Curve Cryptography (ECC), a representative public key cipher. The existing scan attacks on ECC exploit the Design for Testability (DfT) infrastructure of the implementation to identify the internal registers used in the scalar multiplication, and leak the secret key based on a bit-flip analysis in the scalar multiplication registers. These attacks assume two internal registers are affected by the secret key in the ECC. In practical implementations, multiple internal registers are affected by the secret key, significantly complicating the identification of the targeted registers. Furthermore, existing scan attacks rely on a switch from normal to test mode, fail against the widely utilized mode-reset countermeasure. The proposed attack identifies the internal registers in a depth-first search fashion, where registers corresponding to the innermost module of the hardware design are identified first. This attack identifies all the registers related to the secret key, and does so by remaining only in the test mode, thus overcoming both limitations of the existing scan attacks.