{"title":"反向序列化性作为乐观并发控制的正确性标准","authors":"Hyeokmin Kwon, Songchun Moon","doi":"10.1016/0165-6074(94)90035-3","DOIUrl":null,"url":null,"abstract":"<div><p>If buffer retention effect is taken into account, validation schemes for optimistic concurrency control (OCC) should be approached in some different point of view: rather than killing the conflicting transactions immediately in the middle of their execution, it would be better to allow them to run to their completion for bringing the required data objects into main memory. In this respect, we propose a new validation scheme for OCC called <strong><em>reordering serial equivalence</em></strong> (<strong>RSE</strong>) by introducing <em>reverse serializability</em>, which ensures the correctness of RSE when we allow the serialization in the reverse order of transactions' commits.</p></div>","PeriodicalId":100927,"journal":{"name":"Microprocessing and Microprogramming","volume":"40 10","pages":"Pages 759-762"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0165-6074(94)90035-3","citationCount":"1","resultStr":"{\"title\":\"Reverse serializability as a correctness criterion for optimistic concurrency control\",\"authors\":\"Hyeokmin Kwon, Songchun Moon\",\"doi\":\"10.1016/0165-6074(94)90035-3\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>If buffer retention effect is taken into account, validation schemes for optimistic concurrency control (OCC) should be approached in some different point of view: rather than killing the conflicting transactions immediately in the middle of their execution, it would be better to allow them to run to their completion for bringing the required data objects into main memory. In this respect, we propose a new validation scheme for OCC called <strong><em>reordering serial equivalence</em></strong> (<strong>RSE</strong>) by introducing <em>reverse serializability</em>, which ensures the correctness of RSE when we allow the serialization in the reverse order of transactions' commits.</p></div>\",\"PeriodicalId\":100927,\"journal\":{\"name\":\"Microprocessing and Microprogramming\",\"volume\":\"40 10\",\"pages\":\"Pages 759-762\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/0165-6074(94)90035-3\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microprocessing and Microprogramming\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/0165607494900353\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessing and Microprogramming","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0165607494900353","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reverse serializability as a correctness criterion for optimistic concurrency control
If buffer retention effect is taken into account, validation schemes for optimistic concurrency control (OCC) should be approached in some different point of view: rather than killing the conflicting transactions immediately in the middle of their execution, it would be better to allow them to run to their completion for bringing the required data objects into main memory. In this respect, we propose a new validation scheme for OCC called reordering serial equivalence (RSE) by introducing reverse serializability, which ensures the correctness of RSE when we allow the serialization in the reverse order of transactions' commits.