数字集成电路可靠性仿真的年龄感知库

M. Katoozi, E. Cannon, T. Dao, K. Aitken, S. Fischer, T. Amort, R. Brees, J. Tostenrude
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引用次数: 4

摘要

提出了一种用于创建年龄感知细胞库的通用方法,包括多种可靠性退化机制的影响。底层退化模型考虑了影响可靠性的关键参数,如输入摆幅率、输出负载、信号切换率、信号活动因子、输出缓冲区大小和使用时间。本文还讨论了使用该年龄感知库使用现有的电子设计自动化(EDA)方法分析数字集成电路(IC)时序性能老化的框架。
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An age-aware library for reliability simulation of digital ICs
A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account key reliability-impacting parameters such as input slew rate, output load, signal toggle rate, signal activity factor, output buffer size and age. A framework for using this age-aware library to analyze the aging of digital Integrated Circuit (IC) timing performance using existing Electronic Design Automation (EDA) methodologies is also discussed.
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