{"title":"GF(2^163)上高性能椭圆曲线密码系统处理器的改进","authors":"K. C. C. Loi, S. Ko","doi":"10.1109/ISED.2012.15","DOIUrl":null,"url":null,"abstract":"Improvements of the Elliptic Curve Cryptosystem (ECC) point multiplication processor is presented in this paper. The main contributions of this paper are the improved finite field multiplier, which uses a 2-stage Karatsuba-Ofman multiplier architecture. Furthermore, a revised algorithm is proposed for the projective to affine coordinate conversion, which computes 2 inversion operations simultaneously with the numerator portion, in order to make better use of parallel cores implemented in the ECC processor. The design is implemented on a Virtex 4 XC4VLX80 FPGA and the implementation results show that the ECC processor can compute a point multiplication in 6.72 us. This time is the fastest to the authors' best knowledge. Thus, the ECC processor proposed in this paper is suitable for applications where high-throughput is required, such as network servers.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163)\",\"authors\":\"K. C. C. Loi, S. Ko\",\"doi\":\"10.1109/ISED.2012.15\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Improvements of the Elliptic Curve Cryptosystem (ECC) point multiplication processor is presented in this paper. The main contributions of this paper are the improved finite field multiplier, which uses a 2-stage Karatsuba-Ofman multiplier architecture. Furthermore, a revised algorithm is proposed for the projective to affine coordinate conversion, which computes 2 inversion operations simultaneously with the numerator portion, in order to make better use of parallel cores implemented in the ECC processor. The design is implemented on a Virtex 4 XC4VLX80 FPGA and the implementation results show that the ECC processor can compute a point multiplication in 6.72 us. This time is the fastest to the authors' best knowledge. Thus, the ECC processor proposed in this paper is suitable for applications where high-throughput is required, such as network servers.\",\"PeriodicalId\":276803,\"journal\":{\"name\":\"2012 International Symposium on Electronic System Design (ISED)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Symposium on Electronic System Design (ISED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2012.15\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Symposium on Electronic System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2012.15","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163)
Improvements of the Elliptic Curve Cryptosystem (ECC) point multiplication processor is presented in this paper. The main contributions of this paper are the improved finite field multiplier, which uses a 2-stage Karatsuba-Ofman multiplier architecture. Furthermore, a revised algorithm is proposed for the projective to affine coordinate conversion, which computes 2 inversion operations simultaneously with the numerator portion, in order to make better use of parallel cores implemented in the ECC processor. The design is implemented on a Virtex 4 XC4VLX80 FPGA and the implementation results show that the ECC processor can compute a point multiplication in 6.72 us. This time is the fastest to the authors' best knowledge. Thus, the ECC processor proposed in this paper is suitable for applications where high-throughput is required, such as network servers.