ASIC设计可测试性

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit, Pub Date : 1989-09-25 DOI:10.1109/ASIC.1989.123158

D. Braune, D. Ibarra, H. Courjon

{"title":"ASIC设计可测试性","authors":"D. Braune, D. Ibarra, H. Courjon","doi":"10.1109/ASIC.1989.123158","DOIUrl":null,"url":null,"abstract":"Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and comprehensive pattern generation.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"ASIC design for testability\",\"authors\":\"D. Braune, D. Ibarra, H. Courjon\",\"doi\":\"10.1109/ASIC.1989.123158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and comprehensive pattern generation.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

介绍了专用集成电路(ASIC)设计的先进可测试性技术。BIST(内置自检)，扫描测试，边界扫描，嵌入式内核和混合信号电路是讨论的主题之一。CAE方法和具体的案例研究分析了每个ASIC设计选择。重点是测试的模块化设计、自动化的可测试性分析和全面的模式生成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

ASIC design for testability

Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and comprehensive pattern generation.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

自引率

0.00%

发文量

期刊最新文献

BiCMOS ASICs: technology and applications Custom RISC has international applications Synthesis of analog ASICs using optimization in conjunction with circuit simulation techniques ECL ASIC, a practical choice of high performance systems In-circuit-emulation in ASIC architectural core designs