{"title":"一种改进的准方波直流链路变换器","authors":"M. Cavalcanti, E. D. da Silva, C. Jacobina","doi":"10.1109/IAS.2002.1042770","DOIUrl":null,"url":null,"abstract":"This paper proposes a quasi-square-wave DC link (QSWDCL) converter, which improves the performance of an existing topology. The proposed circuit provides zero-DC-link voltage notches, during which the inverter switching is effected, and imposes a minimum DC bus voltage stress to the PWM inverter. Simple design conditions are offered. Simulated and experimental results demonstrate the validity of the proposed topologies.","PeriodicalId":202482,"journal":{"name":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An improved quasi-square-wave DC-link converter\",\"authors\":\"M. Cavalcanti, E. D. da Silva, C. Jacobina\",\"doi\":\"10.1109/IAS.2002.1042770\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a quasi-square-wave DC link (QSWDCL) converter, which improves the performance of an existing topology. The proposed circuit provides zero-DC-link voltage notches, during which the inverter switching is effected, and imposes a minimum DC bus voltage stress to the PWM inverter. Simple design conditions are offered. Simulated and experimental results demonstrate the validity of the proposed topologies.\",\"PeriodicalId\":202482,\"journal\":{\"name\":\"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IAS.2002.1042770\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAS.2002.1042770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper proposes a quasi-square-wave DC link (QSWDCL) converter, which improves the performance of an existing topology. The proposed circuit provides zero-DC-link voltage notches, during which the inverter switching is effected, and imposes a minimum DC bus voltage stress to the PWM inverter. Simple design conditions are offered. Simulated and experimental results demonstrate the validity of the proposed topologies.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
