双向交流耦合接口与自适应扩频时钟发生器

Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa
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引用次数: 5

摘要

我们提出了一种利用双向和交流耦合接口的自适应扩频时钟锁相环(SSC-PLL)电路来降低量化噪声和频谱峰值的方法。为了实现高速、宽范围、双向和长电缆收发,我们设计了一个测试芯片,包含均衡器、CDR和长电缆差分收发器,以及一个ssc锁相环,通过自适应带宽设置优化抖动来降低频谱峰值。利用该接口,可以实现高达810 Mbps和20 m的双向收发系统,具有高ESD保护,并在最佳带宽下有效地降低了-23 dB左右的频谱峰值。
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Bi-directional AC coupled interface with adaptive spread spectrum clock generator
We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.
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