Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa
{"title":"双向交流耦合接口与自适应扩频时钟发生器","authors":"Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa","doi":"10.1109/ASSCC.2007.4425734","DOIUrl":null,"url":null,"abstract":"We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Bi-directional AC coupled interface with adaptive spread spectrum clock generator\",\"authors\":\"Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa\",\"doi\":\"10.1109/ASSCC.2007.4425734\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425734\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bi-directional AC coupled interface with adaptive spread spectrum clock generator
We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.