A novel FPGA design of a high throughput rate adaptive prediction error filter

In this paper we propose a novel adaptive prediction error filter design and implement it as a DSP core on FPGAs. The filter consists of a predictor and a Toeplitz solver. Previous ASIC design approaches often encountered problems such as unbalanced computing loads and extra data redirection circuit overheads. Therefore, we first reformulate the Schur algorithm and then derive an efficient systolic array designs capable of solving a size N Toeplitz matrix in every 2N cycles with each cycle equal to one MAC delay. The predictor design is implemented using the distributed arithmetic (DA) approach. The entire design is described in synthesizable VHDL code and fully parameterized with respect to the matrix size and word length. For the case of solving a tap 50 adaptive prediction error filter, we can achieve a clock rate of 40 MHz and a processing (symbol) rate as high as 60,976 matrix updates per second using four Xilinx 4044XL-3 FPGAs.