A Hierarchical Sensing Scheme (HSS) Of High-density And Low-voltage Operation SRAMs

This paper proposes a new hicrarchical sensing scheme (HSS) that realizes stability in READ/WRITE operation for a small SRAM memory cell. By adopting the HSS, highdensity and low-voltage operation SRAMs with a small diesize, which is suitable for mobile multi-media devices, can be realized. The HSS makes best use of Cb/Cs relation in the circuit design. The simulation show that the HSS SRAM functions satisfactory with a cell ratio of 1.5 (< 50% of conventional) at Vcc = 3V and 2.5 at Vcc = 1.8V. 1, Introduct ion As portable machinery such as handy terminals and lap-top personal computers increase their market share, the demand for high-density and low-voltage operation memories has increased. A large cell ratio such as 3 to 4 is necessary for stablc memory cell operation. Therefore, 3 to 4 times large transistor has to be integrated in a memory cell. Because of this large cell ratio requirement, it is difficult to realize a high-density SRAM. For a low-voltage operation, the six-transistor full-CMOS cell [l] or the boosted word line technique [21 are used. These technologies, however, require a larger die size or elaborated circuits and fabrication processes. This paper proposes a hierarchical sensing scheme (HSS) that make both high-density and low-voltage operation possible for SRAMs with smaller memory cells. 2. Hierarchical Sensine Scheme (HSS)