Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich
{"title":"高效卷积神经网络用于脑电信号伪影检测","authors":"Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich","doi":"10.1109/BIOCAS.2018.8584791","DOIUrl":null,"url":null,"abstract":"This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.","PeriodicalId":259162,"journal":{"name":"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Energy Efficient Convolutional Neural Networks for EEG Artifact Detection\",\"authors\":\"Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich\",\"doi\":\"10.1109/BIOCAS.2018.8584791\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.\",\"PeriodicalId\":259162,\"journal\":{\"name\":\"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)\",\"volume\":\"110 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIOCAS.2018.8584791\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIOCAS.2018.8584791","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Energy Efficient Convolutional Neural Networks for EEG Artifact Detection
This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.