高效卷积神经网络用于脑电信号伪影检测

Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich
{"title":"高效卷积神经网络用于脑电信号伪影检测","authors":"Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich","doi":"10.1109/BIOCAS.2018.8584791","DOIUrl":null,"url":null,"abstract":"This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.","PeriodicalId":259162,"journal":{"name":"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Energy Efficient Convolutional Neural Networks for EEG Artifact Detection\",\"authors\":\"Mohit Khatwani, M. Hosseini, Hirenkumar Paneliya, T. Mohsenin, W. Hairston, Nicholas R. Waytowich\",\"doi\":\"10.1109/BIOCAS.2018.8584791\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.\",\"PeriodicalId\":259162,\"journal\":{\"name\":\"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)\",\"volume\":\"110 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIOCAS.2018.8584791\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIOCAS.2018.8584791","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

摘要

针对多通道脑电信号中不同类型伪影的检测问题,提出了一种基于卷积神经网络的高能效结构。我们的方法在七种不同的工件类型中实现了74%的平均工件检测准确率和92%的精度,在分类精度方面优于现有技术,在计算复杂性和内存要求方面优于更常见的基于ICA的解决方案。我们设计了一个最小的神经网络处理器,其Verilog HDL可配置用于实现2n处理引擎(pe)。我们将CNN部署在处理器上,在Artix-7 FPGA上放置和路由,并在不同的工作频率下检查不同数量的pe。我们的实验表明,使用4个以11.1 MHz时钟频率工作的pe是我们硬件的最佳配置,可以在1秒的最大允许预测时间内产生最小的分类能耗32 mJ。我们还在TX2 NVIDIA平台上实现了我们的CNN,并通过调整CPU和GPU频率,探索了最低功耗配置和另一种最低能耗配置。我们的FPGA结果表明,4-PE实现优于低功耗配置。TX2的功率降低了65倍,低能耗配置。将TX2的能量除以2倍。我们基于cnn的FPGA实现方法在每个分类的能耗方面也优于ICA方法11倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Energy Efficient Convolutional Neural Networks for EEG Artifact Detection
This paper proposes an energy efficient Convolutional Neural Network based architecture for detecting different types of artifacts in multi-channel EEG signals. Our method achieves an average artifact detection accuracy of 74% and precision of 92% across seven different artifact types which outperforms existing techniques in terms of classification accuracy as well as the more common ICA based solution in terms of computational complexity and memory requirements. We designed a minimal neural network processor whose Verilog HDL is configurable for implementing 2n processing engines (PEs). We deployed our CNN on the processor, placed and routed on Artix-7 FPGA and examined different number of PEs at different operating frequencies. Our experiments indicate that utilizing 4 PEs operating at a clock frequency of 11.1 MHz is the optimal configuration for our hardware to yield the least classification energy consumption of 32 mJ accomplished in the maximum allowed prediction time of 1 Sec. We also implemented our CNN on TX2 NVIDIA platform and, by tweaking the CPU and the GPU frequencies, explored a least power configuration and another least energy consuming configuration. Our FPGA results indicate that the 4-PE implementation outperforms the low power config. of TX2 by 65× in terms of power, and the low energy config. of TX2 by 2× in terms of energy per classification. Our CNN-based FPGA implementation method also outperforms the ICA method by 11× in terms of energy consumption per classification.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Smart Prosthesis System: Continuous Automatic Prosthesis Fitting Adjustment and Real-time Stress Visualization Framework of Applying Independent Component Analysis After Compressed Sensing for Electroencephalogram Signals Live Demonstration: A Bluetooth Low Energy (BLE)-enabled Wireless Link for Bidirectional Communications with a Neural Microsystem The Spectral Calibration of Swept-Source Optical Coherence Tomography Systems Using Unscented Kalman Filter An Ultra-Wideband-Inspired System-on-Chip for an Optical Bidirectional Transcutaneous Biotelemetry
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1