Advanced technology for improved signal processor efficiency

Wafer scale integration technology offers the promise of implementing application specific processors with significantly higher data rates, lower power, and smaller size than conventional VLSI implementations. Wafer scale integration implementations replace most of the signal lines between chips with intra-wafer lines that exhibit one to two orders of magnitude less stray capacitance so they may be driven at higher rates while consuming much less power. Application specific processors implemented with regular arrays of processing elements are attractive because their regularity simplifies the design, fabrication, and circumvention of faulty elements. This paper shows that one dimensional systolic arrays are more attractive for this application than other regular architectures. This paper also shows that (1:N) and (M:N) pooled sparing at the macrocell level is feasible to overcome the defects implicit in the fabrication process. Finally an example design for a systolic FFT processor is described to illustrate the wafer scale implementation of a signal processor.<>