{"title":"LVCMOS高分辨率频率合成器的设计","authors":"F. Lobato-Lopez, S. Solis-Bustos, H. Sucar","doi":"10.1109/ICCDCS.2002.1004005","DOIUrl":null,"url":null,"abstract":"This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of an LVCMOS high resolution frequency synthesizer\",\"authors\":\"F. Lobato-Lopez, S. Solis-Bustos, H. Sucar\",\"doi\":\"10.1109/ICCDCS.2002.1004005\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.\",\"PeriodicalId\":416680,\"journal\":{\"name\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCDCS.2002.1004005\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2002.1004005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an LVCMOS high resolution frequency synthesizer
This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.
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