A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme

This paper demonstrates that an Interleaved Synchronous Mirror delay (I-SMD) drastically reduces jitter in CMOS digital clock generators. I-SMD jitter reduction process consists of (1) SMD's inherent characteristics, (2) interleaving, and (3) their synergistic jitter suppression effect using an OR type MUX. Simulation results based on a tpd=300ps CMOS process demonstrate that the quadruple I- SMD achieves a jitter=lOps. The results also demonstrate that an optimized I-SMD reduces jitter without increasing circuit size or power consumption.