采用混合SET-MOS技术的面积高效三元全加法器

2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO) Pub Date : 2017-07-01 DOI:10.1109/NANO.2017.8117301

Lin Li, Zihan Zhang, Chunhong Chen

{"title":"采用混合SET-MOS技术的面积高效三元全加法器","authors":"Lin Li, Zihan Zhang, Chunhong Chen","doi":"10.1109/NANO.2017.8117301","DOIUrl":null,"url":null,"abstract":"This paper presents a novel design of ternary full adder (TFA) using hybrid single-electron transistor (SET) and MOS technology. The proposed circuit is evaluated using the Cadence Spectre simulator with 180nm CMOS technology and SET macro models under various test conditions. Results show that the proposed TFA dramatically reduces the number of transistors required with little or no loss in energy efficiency.","PeriodicalId":292399,"journal":{"name":"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An area-efficient ternary full adder using hybrid SET-MOS technology\",\"authors\":\"Lin Li, Zihan Zhang, Chunhong Chen\",\"doi\":\"10.1109/NANO.2017.8117301\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel design of ternary full adder (TFA) using hybrid single-electron transistor (SET) and MOS technology. The proposed circuit is evaluated using the Cadence Spectre simulator with 180nm CMOS technology and SET macro models under various test conditions. Results show that the proposed TFA dramatically reduces the number of transistors required with little or no loss in energy efficiency.\",\"PeriodicalId\":292399,\"journal\":{\"name\":\"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NANO.2017.8117301\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2017.8117301","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文提出了一种利用单电子晶体管(SET)和MOS混合技术设计的三元全加法器(TFA)。在各种测试条件下，利用采用180nm CMOS技术的Cadence Spectre模拟器和SET宏观模型对所提出的电路进行了评估。结果表明，所提出的TFA显着减少了所需的晶体管数量，而能量效率几乎没有损失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An area-efficient ternary full adder using hybrid SET-MOS technology

This paper presents a novel design of ternary full adder (TFA) using hybrid single-electron transistor (SET) and MOS technology. The proposed circuit is evaluated using the Cadence Spectre simulator with 180nm CMOS technology and SET macro models under various test conditions. Results show that the proposed TFA dramatically reduces the number of transistors required with little or no loss in energy efficiency.

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2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)

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