VTEG: VHDL test environment generator

The consumer electronics market is flooding with new emhedded system products. Programmable logic devices (PLDs) are. most ofthe lime. un integra1pur.l of these con.szmier prodzicrs. With ever-increasing comp1e.rit.v in Hardwure design language (HDL) based designs Jbr PLDs, and driven hv /he pressure,fbr time to market. designers and res/ engineer.^ wan/.fosl Jimclional verification of /heir HDL hased designs. This paper discusses the VTEG tool. which is an upprouch ro anlomute a generic lest hench environment. which can he used across HDL modules/zmit.s. With the inre+ce derails of the design as input, /he VTEG tool generates VHDL modules for driving and monitoring interfaces of rhe design. The motivarion behind /he development of /he tool is to uutomnte tesr-hench generation. easy exrendihility of the test hench in case of design chbnges. better tesr hench maintenance. and better understandahi1it.v for reuse purposes. This tool is aimed to reduce the cycle time of test bench genevation for verification of HDL designs resulting bi improvemenf of design productivity. Index Terms Automation, Verification, VHDL, Test-Bench, HDL.