{"title":"用于频率转换的CORDIC旋转器","authors":"A. I. Smekalov, V. Djigan","doi":"10.1109/EWDTS.2016.7807701","DOIUrl":null,"url":null,"abstract":"This paper presents a digital frequency translation by the CORDIC rotator (COordinate Rotation DIgital Computer) which does not require a complex multiplier and a phase-to-exponent converter. The CORDIC algorithm overview and detailed implementation architecture are presented. The architecture is fitted to implementation in high speed designs and using in Application-Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA). The simulation results demonstrate the performance of proposed frequency translator in terms of Normalized Mean-Square Error (NMSE) and spectral purity. The proposed architecture requires about 79 times less resources compared to the conventional approach with a complex multiplier and Numerically Controlled Oscillator (NCO) at the same level 98 dB of Spurious Free Dynamic Range (SFDR).","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CORDIC rotator for frequency translation\",\"authors\":\"A. I. Smekalov, V. Djigan\",\"doi\":\"10.1109/EWDTS.2016.7807701\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital frequency translation by the CORDIC rotator (COordinate Rotation DIgital Computer) which does not require a complex multiplier and a phase-to-exponent converter. The CORDIC algorithm overview and detailed implementation architecture are presented. The architecture is fitted to implementation in high speed designs and using in Application-Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA). The simulation results demonstrate the performance of proposed frequency translator in terms of Normalized Mean-Square Error (NMSE) and spectral purity. The proposed architecture requires about 79 times less resources compared to the conventional approach with a complex multiplier and Numerically Controlled Oscillator (NCO) at the same level 98 dB of Spurious Free Dynamic Range (SFDR).\",\"PeriodicalId\":364686,\"journal\":{\"name\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2016.7807701\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2016.7807701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文提出了一种利用坐标旋转数字计算机(CORDIC rotator, COordinate Rotation digital Computer)进行数字频率转换的方法,该方法不需要复乘法器和相位指数转换器。给出了CORDIC算法概述和详细的实现体系结构。该体系结构适用于高速设计和专用集成电路(ASIC)或现场可编程门阵列(FPGA)。仿真结果证明了该频率转换器在归一化均方误差(NMSE)和频谱纯度方面的性能。在相同的无杂散动态范围(SFDR)为98 dB的水平上,与传统的复杂乘子和数控振荡器(NCO)相比,该架构所需的资源减少了约79倍。
This paper presents a digital frequency translation by the CORDIC rotator (COordinate Rotation DIgital Computer) which does not require a complex multiplier and a phase-to-exponent converter. The CORDIC algorithm overview and detailed implementation architecture are presented. The architecture is fitted to implementation in high speed designs and using in Application-Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA). The simulation results demonstrate the performance of proposed frequency translator in terms of Normalized Mean-Square Error (NMSE) and spectral purity. The proposed architecture requires about 79 times less resources compared to the conventional approach with a complex multiplier and Numerically Controlled Oscillator (NCO) at the same level 98 dB of Spurious Free Dynamic Range (SFDR).